This invention relates generally to oversampled analog to digital converters that convert an analog input to a digital output suitable for use by a variety of digital circuits including processors.
An analog to digital converter may be an important circuit because it interfaces the real world with digital logic. For example, the human voice is inherently an analog signal that may be converted to a digital signal before it may be processed by a digital signal processor or a microprocessor. However, the performance of many analog to digital converter architectures is significantly affected by process variations, such as the resistance or capacitance variations inherent in weighting networks used with successive approximation or dual ramp conversion techniques.
Analog to digital converters may be based on oversampling techniques for higher resolution. The analog to digital converter using oversampling may operate at a clock rate that is higher than the data rate of the oversampled analog signal. Oversampling analog to digital converters may use delta-sigma modulators, to noise shape a bit stream and to develop a pulse density proportional to the analog signal""s amplitude.
The delta-sigma architecture is robust for process variations using oversampling and decimation. Therefore, the delta-sigma architecture may not need high precision resistor or capacitor weighting networks. As a result, delta-sigma analog to digital converters are the prevailing technique for use in voice, audio and instrumentation applications.
The delta-sigma modulator receives an analog input and a high speed sampling clock. Its output is filtered to eliminate modulation noise. Also, because the output of the delta-sigma modulator has a high sampling rate, it is normally decimated to generate the final digital output at the desired frequency. The ratio between the delta-sigma modulator sampling rate and the output frequency is called the oversampling ratio.
For a variety of electronic applications, there are international standards for the signal band and output sampling rate. As one example, one international standard for voice coding for communication currently requires an output sampling rate of eight kilohertz. In order to have an eight kilohertz output sampling rate, the oversampling ratio should be an integer multiplication of eight kilohertz.
A problem arises when the system clock is not an integer multiplication of the desired output signal frequency. Suppose in a voice coder/decoder, or codec, the system clock is thirteen megahertz and the output sampling rate must be eight kilohertz pursuant to a standard. The decimation ratio is thirteen megahertz divided by thirty-two kilohertz (which is the output of a sinc filter) or 406.25. Since the design of digital logic to achieve a decimation ratio 406.25, is not viable, it would be desirable to achieve a sampling rate that is a multiple of eight kilohertz in this example.
The conventional solution to this dilemma is to design a phase-locked loop (PLL) and to generate the needed sampling clock to the delta-sigma modulator. For example, a phase-locked loop with an eight megahertz clock rate will enable the delta-sigma modulator to output a data rate of eight megahertz. This output may be filtered to thirty-two kilohertz and then decimated to eight kilohertz, as one example.
The use of a phase-locked loop may increase design time, take up silicon area and require more testing. Thus, there is a need for a technique to achieve a desired output sampling rate when the system clock is not an integer multiplication of the desired output sampling rate without using a phase-locked loop.